Static random access memory (SRAM) devices are used in a wide variety of memory applications, frequently in applications where high speed performance is important. As is well-known to those skilled in the art, traditional SRAM circuits typically include a bistable transistor cell which includes a pair of cross-coupled transistors which switch current from a power supply voltage through fixed resistor loads. However, the use of fixed resistors can limit the switching speed of the cell due to the time constant associated with the fixed resistors. Increasing the speed at which such an SRAM cell is accessed can lead to an increased number of "soft errors", i.e., misreadings of the SRAM cell.
To avoid such problems, SRAM cells have been developed which use a cross-coupled complementary transistor circuit such as that illustrated in FIG. 1, which includes a pair of driving transistors 2, 4 which drive a pair of complementary load transistors 10, 12. Because the load transistors 10, 12 present a small resistance when biased in an "on" state, switching times may be reduced without undesirably increasing the probability of soft errors. In addition, the complementary cell of FIG. 1 tends to be more stable and less vulnerable to soft errors under a low standby current and voltage.
The driving transistors 2, 4 typically are fabricated as substrate transistors. For example, as illustrated in FIG. 2, a driving transistor may be a field effect transistor having source/drain regions 23, 25 formed in a substrate 21 on opposite sides of a channel region 27, with a gate electrode 29 formed on the surface of the substrate, controlling current flowing between the source and drain regions. The load transistors 10, 12 typically are fabricated as thin film transistors, for example, source/drain and channel regions 35, 33 formed from a semiconductor layer formed on a gate electrode 31.
Although the cell illustrated in FIG. 2 is formed from a small number of polycrystalline silicon layers, it has a relatively complex structure. As the size of the cell is decreased, fabrication, in particular, the interconnection of the gate electrodes 31, 29, may become more difficult. The increased difficulty in fabricating such a complex cell structure as its size is reduced can lead to poor yields and increased production costs.